The present invention relates to multi-processing systems and, more particularly, to communication bus structures for communicating transactions in a multi-processing system.
In data processing and communications systems it is common for a global communication bus to be utilized to connect the various components and modules of the system. Such components include, inter alia, processors, memory controllers and peripheral controllers for controlling peripherals such as keyboards, Small Computer System Interface (SCSI) connections and Ethernet connections. In addition, a bus arbitration unit must be connected to common communication bus for controlling accesses to the bus. The implementation of such systems are typically specific to one type of bus arbitration scheme and one type of bus protocol.
Shown in FIG. 1 is a data processing system 10 which is representative of the present state of multi-processing systems. A global bus 12 is coupled to a first processing element 14, to a second processing element 16 and to a third processing element 17. A memory controller 18 is also coupled to global bus 12. Memory controller 18 is separately coupled to a memory 20. A bus arbitration unit 22 is coupled to global bus 12. A number of peripheral controllers including a first peripheral controller 24 through an Nth peripheral controller 28, where N is an integer, is coupled to global bus 12. A keyboard 26 is coupled to peripheral controller 24, and an ethernet connection 30 is coupled to peripheral controller 28. A bus bridge 32 is shown coupled between global bus 12 and a subordinate bus 34. A second bus arbitration unit 36 is coupled to the subordinate bus 34. Both a fourth processing element 38 and a peripheral controller 40 are coupled to subordinate bus 34. Peripheral controller 40 is coupled to a SCSI port 42.
Bus arbitration unit 22 functions to control which of the numerous potential bus masters coupled to global bus 12 will have control of the global bus 12 and for how long. The bus arbitration function for global bus 12 is centralized within bus arbitration unit 22. Numerous bus arbitration techniques exist. A typical feature of all known forms of bus arbitration unit 22 is that bus arbitration unit 22 must contain the logic circuitry associated with the bus protocol which is selected for global bus 12. Each of the peripherals from global bus 12 must be appropriately specified to a common defined bus specification or protocol. Each bus protocol may be unique in the way operations, such as a data read and a data write, are ordered. Protocols are also specific as to how requests for servicing are handled in relation to how responses to such requests are made. The implementation of a specific protocol in bus arbitration unit 22 results in several disadvantages. Firstly, once a bus protocol for global bus 12 is chosen and implemented, any additional peripheral units which are to be added to the system for using that bus must implement that bus protocol in order to be compatible in the system. This constraint necessitates the addition of a bus bridge such as bus bridge 32 should any additional peripherals using a different bus protocol be added to the system. Additionally, another bus arbitration unit 36 is required to be added to the system should multiple peripherals, such as processing element 38 and peripheral controller 40, be coupled to the subordinate bus 34. These disadvantages plus the extra circuitry required in each of the peripherals and the bus arbitration units 22 to implement a selected bus protocol, such as the well known standard bus protocols PCI (Peripheral Component Interconnect) or VME, significantly add to the cost of a multi-processing system as well as increase the physical size of the system.
Other data processing systems having multiple bus masters are known in which a central positioned interconnect is used having multiple inputs for communicating simultaneously with each bus master. In such systems, the bus arbitration function and the bus protocol logic must be implemented in the interconnect device and thus a large amount of dedicated circuitry is required in addition to bus protocol logic in each bus master. If multiple interconnect devices are used to distribute the bus distribution functionality, the bus protocol logic circuitry has to be implemented in each interconnect device. Additionally, such systems are susceptible to reaching a deadlock condition where the interconnect cannot newly received transactions because pending transactions cannot be completed. There exists therefore a need for a simpler and more flexible method and mechanism for implementing bus transactions in a multi-processing system capable of proper handling of transaction ordering while avoiding deadlock conditions.